The present invention relates to a system for updating an inactive system memory in a duplex processing apparatus having duplexed packages, each incorporating a microprocessors.
A duplex processing apparatus is known in which, to improve the reliability of a system to which the apparatus is applied, two packages, each incorporating a microprocessor and having a data processing function, are duplexed. Such a duplex processing apparatus has two identical packages. With this arrangement, even if one package is stopped because of a failure or the like, the other package takes over the processing. Therefore, the overall function is not easily corrupted and a highly reliable apparatus can be realized. In an apparatus having packages duplexed, the contents of a memory of an active system package must be identical to those of a memory of an inactive system package.
FIG. 3 shows the arrangement of an information processing apparatus in which packages are duplexed in this manner. Referring to FIG. 3, reference numeral 21 denotes a CPU (Central Processing Unit), of a package A, which is a microprocessor; 22, a CPU of a package B, which is a microprocessor; 23, a memory connected to the CPU 21; 24, a memory connected to the CPU 22; 25, a buffer of the package A, which is connected between the CPU 21 and the package B; 26, a buffer of the package B, which is connected between the CPU 22 and the package A; 27, a selection circuit of the package A, which serves to select the CPU 21 or the buffer 26; and 28, a selection circuit of the package B, which serves to select the CPU 22 or the buffer 25.
The CPUs 21 and 22 and the buffers 25 and 26 are connected to each other via data buses 31, address busses 32, and control buses 33. The CPUs 21 and 22 and the memories 23 and 24 are also connected through the selection circuits 27 and 28 via the above buses. The buffer 25 and the selection circuit 28 of the package B are connected to each other via the data bus 31, the data bus 32, and the control bus 33, so are the buffer 26 and the selection circuit 27 of the package A. That is, the selection circuit 28 receives data and control signals from the CPUs 21 and 22.
The selection circuits 27 and 28 connect the memory 23 to one of the CPUs 21 and 22 which is in an active state in accordance with a monitor signal indicating which specific one of the CPUs 21 and 22 is in an active state. If, for example, the package A is in an active state, the CPU 21 is ready to perform processing. Therefore, the selection circuit 27 connects the memory 23 to the CPU 21, and the selection circuit 28 of the package B connects the memory 24 to the CPU 21 via the buffer 25. With this connection, the CPU 21 can update identical data in the memories 23 and 24 so that the memories 23 and 24 always hold the same contents.
In the conventional duplex processing apparatus having the above arrangement, since the CPU 21 in an active state must perform update processing of data in the memory 24 as well as update processing of data in the memory 23, the load on the CPU 21 is heavy.